1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to various methods of correcting non-linearity of metrology tools, and a system for performing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating performance of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Moreover, the density of such transistors on a wafer per unit area has dramatically increased as a result of, among other things, the reduction in feature sizes, and an overall desire to minimize the size of various integrated circuit products.
By way of background, modern integrated circuit devices, e.g., microprocessors, ASICs, memory devices, etc., are comprised of millions of field effect transistors formed on a semiconducting substrate, such as silicon. The substrate may be doped with either N-type or P-type dopant materials. An illustrative field effect transistor 10, as shown in FIG. 1, may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit product is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Thus, it is very important that the critical dimension 12 of the gate electrode 14 be formed very accurately. Even small errors in the critical dimension 12 of the gate electrode 14 can result in the failure of the finished product to meet certain target electrical performance characteristics, e.g., switching speed, leakage current, etc. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
As device dimensions have continued to shrink, the packing density of the semiconductor devices, e.g., transistors, has increased. That is, ever increasing numbers of transistors or memory cells are located on the same plot space of a semiconducting substrate. As a result of this increased device density, the conductive metal lines and contacts or vias that connect these various devices have also been reduced in physical size, and they are also packed more closely together. In general, the resistance of a metal line is inversely proportional to the cross-sectional area of the metal line. Thus, all other things being equal, it is important that the cross-sectional area of the metal line be maintained above certain minimum levels such that the resistance of the metal line does not exceed allowable limits. Unanticipated increases in the resistance of a metal line may adversely impact device performance, e.g., a reduction in operating frequency, increased heat build-up, increased power consumption, etc.
In recent years, improvement in manufacturing techniques have enabled integrated circuit manufacturers to produce features, e.g., gate electrodes, metal lines, etc., with very small physical dimensions. For example, using current technology, the critical dimension 12 of a gate electrode 14 for a transistor 10 in a high performance microprocessor may be approximately 120-180 nm, and further reduction in the size or scale of such features is anticipated in the future. Unfortunately, as feature sizes continue to decrease, it becomes very difficult to accurately measure such features with the requisite degree of precision. This can be very problematic in that even very small variations in the size of the features may have an adverse impact on device performance and profitability.
For example, after a group of integrated circuit devices are manufactured, they may be subjected to one or more electrical performance tests to determine an electrical characteristic, e.g., switching speed, of the device. Based upon these tests, it may be determined the devices are not operating fast enough. As a result, it may be decided that the critical dimension 12 of the gate electrode 14 structures for the next group of devices to be manufactured needs to be reduced from 100 nm (the critical dimension for the original group of devices) to 98 nm. However, if, due to errors in obtaining metrology data, the features are manufactured with a critical dimension 12 of 98.5 nm, then the finished devices will not exhibit the desired electrical performance characteristic, i.e., increased operating speed. As a result, a number of wafers may be processed wherein the resulting devices do not meeting the targeted electrical performance characteristics.
A variety of metrology tools, e.g., CD scanning electron microscopes (SEM), tunneling electron microscopes (TEM), an optical overlay tool, and a film thickness measurement tool such as an optical-based tool or a profilometer, tend to provide very accurate data over a limited range of measurements. The more the metrology tools are used outside of this range, the greater the error in the measurement data. Stated another way, the metrology tools exhibit non-linear characteristics. Typically, in an effort to overcome or compensate for such non-linearity, metrology tools are finely tuned to measure features having a very small range of sizes. For example, a particular CD-SEM may be tuned to measure gate electrode features having a critical dimension range of 100-120 nm. If the metrology tool is employed to measure feature sizes outside of this range, the metrology tool may need to be re-tuned for the new range of feature sizes. Alternatively, separate metrology tools may be provided wherein the separate tools are each tuned to measure features having different size ranges. Such tuning and the use of multiple metrology tools can be time-consuming and wasteful of manufacturing resources.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to various methods of correcting non-linearity in metrology tools, and a system for performing same. In one illustrative embodiment, the method comprises creating a non-linear model of measurement data produced by a metrology tool when measuring a plurality of features, each of which have a different, known feature size, measuring a production feature using the metrology tool to produce metrology data for the production feature, determining a correction factor to be applied to the metrology data for the production feature by comparing the non-linear model to a linear model, and applying the determined correction factor to the metrology data for the production feature.
In another illustrative embodiment, the method comprises creating a non-linear model of measurement data produced by a metrology tool when measuring a plurality of features, each of which have a different, known feature size, measuring a production feature formed above a semiconducting substrate using the metrology tool to produce metrology data for the production feature, providing the metrology data for the production feature to a controller that determines a correction factor to be applied to the metrology data for the production feature by comparing the non-linear model to a linear model, and applying the determined correction factor to the metrology data for the production feature.
In yet another illustrative embodiment, the method comprises creating a non-linear model of measurement data produced by a scanning electron microscope when measuring a plurality of features, each of which have a different, known feature size, measuring a production feature using the scanning electron microscope to produce metrology data for the production feature, providing the metrology data for the production feature to a controller that determines a correction factor to be applied to the metrology data for the production feature by comparing the non-linear model to a linear model, and applying the determined correction factor to the metrology data for the production feature.